The present invention relates to a subscriber line interface circuit for telecommunication switching systems, and more particularly to a line interface circuit having an impedance synthesizer for synthesizing a termination impedance of the subscriber line.
Subscriber line interface circuits are required to feed loop current as well as to synthesize a termination impedance for signal transmission.
The impedance synthesizer, as shown and described in U.S. patent application Ser. No. 565,975, filed Dec. 27, 1983, comprises a pair of output power amplifiers that drive a pair of reference resistors coupled respectively to input terminals, an amplifier for detecting an input voltage, and an impedance synthesizer for synthesizing a termination impedance. The impedance Zin as seen from the input terminals is given by: EQU Zin=2Ro/(1-G.sub.1)
where Ro is the resistance value of the reference resistors, and G.sub.1 is the transfer function of the output power amplifiers which is selected so that Zin=Zt where Zt is a desired impedance value. The transfer function is given by: EQU G.sub.1 =1-(Zt/2Ro)
To simplify circuitry, the power amplifiers are split into a first feedback loop having a unity loop gain in which high precision is required and a second feedback loop having a loop gain of -Zt/2Ro in which precision is not required, so that overall precision is improved. However, two operational amplifiers of high precision are still required. Particularly, in the case of an interface circuit of the type having a balanced output, at least three high precision operational amplifiers are required and each operational amplifier must meet tight tolerances and wide bandwidth frequency response requirement.